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[VHDL-FPGA-Verilog] asy_FIFO

Description: 用Verilog实现FIFO的异步设计，里面有详细的代码和各个模块的代码，经过调试可以使用-asynchronous FIFO design
Platform: | Size: 3072 | Author: fifo.v | Hits:

[VHDL-FPGA-Verilog] Decoy

Description: 外部 FIFO 的控制 verilog语言-verilog FIFo
Platform: | Size: 1024 | Author: xuxf | Hits:

[VHDL-FPGA-Verilog] fifo_syn

Description: 本源码是用VERILOG实现FIFO的读取，并在实验板上已经验证可以使用-This source is used to achieve FIFO read VERILOG, and the board has been verified in experiments using
Platform: | Size: 19456 | Author: zhao | Hits:

[VHDL-FPGA-Verilog] HighSpeedFIFOsInSpartan-IIFPGAs

Description: This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan™ -II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be changed if the control logic is changed accordingly. Both a common-clock version and an independent-clock version are described.
Platform: | Size: 30720 | Author: fjmwu | Hits:

[VHDL-FPGA-Verilog] sdfsdFifo

Description: 这是一个异步fifo的Verilog 代码，该代码的功能是实现异步的first in first out-This is an asynchronous fifo in the Verilog code, the code' s function is to achieve asynchronous first in first out
Platform: | Size: 1024 | Author: Yongjie | Hits:

[VHDL-FPGA-Verilog] LZY

Description: 基于FPGA的软FIFO代码实现，双时钟，异步。VERILOG-FPGA-based soft FIFO code, two clocks, asynchronous. VERILOG
Platform: | Size: 3072 | Author: liuzongyi | Hits:

[VHDL-FPGA-Verilog] USB_SLAVE_700AN_RD

Description: 基于verilog 代码的USB2.0同步FIFO读代码-USB2.0 syn FIFO read
Platform: | Size: 1024 | Author: austin | Hits:

[VHDL-FPGA-Verilog] sync_fifo

Description: 一种同步的先入先出verilog程序，可正确地通过编译-a programe of fifo wrote by verilog
Platform: | Size: 4096 | Author: ningbo | Hits:

[VHDL-FPGA-Verilog] fifo_verilog

Description: 用verilog 实现 fifo，宽度按自己需求扩展-Achieved with the verilog fifo, the width of expansion according to their needs
Platform: | Size: 4096 | Author: 张小琛 | Hits:

[VHDL-FPGA-Verilog] IPcore_fifo_testbench

Description: 我自己写的一个verilog的fifo测试程序，配合xilinx的fifo ip核-I own the fifo write a verilog test procedures, with the fifo ip nuclear xilinx
Platform: | Size: 1024 | Author: 张学锋 | Hits:

[VHDL-FPGA-Verilog] UART_FIFO

Description: Verilog 语言描述，基于FIFO设计的UART。Quartus 10中编译通过-Verilog language description, based on the design of the UART FIFO
Platform: | Size: 509952 | Author: 老虎 | Hits:

[VHDL-FPGA-Verilog] asy_fifo

Description: 用verilog实现异步fifo，通过仿真-Asynchronous with verilog fifo, the simulation
Platform: | Size: 1024 | Author: lily | Hits:

[VHDL-FPGA-Verilog] foio

Description: verilog语言写的先进先出（FIFO）电路-verilog language written in FIFO (FIFO) circuit
Platform: | Size: 7168 | Author: 黄林 | Hits:

[VHDL-FPGA-Verilog] SPI

Description: 含有fifo缓冲器的SPI接口源代码，用verilog语言实现-SPI Interface fifo buffer containing the source code, using verilog language
Platform: | Size: 49152 | Author: hechunzhi99 | Hits:

[VHDL-FPGA-Verilog] uartfifo

Description: 用 Verilog语言编写的串口发送接收程序，带FIFO 已调试通过-Verilog language with sending and receiving serial program with debugging through the FIFO
Platform: | Size: 806912 | Author: 小涵 | Hits:

[VHDL-FPGA-Verilog] my_FIFO

Description: FIFO的verilog实现，成功通过验证，很好用需要的可以下载-Verilog implementation of FIFO successfully validated, the good need can be downloaded
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] rx_fifo

Description: verilog语言写的接收机FIFO，适用于xilinx环境-verilog language to write the receiver FIFO, the environment for xilinx
Platform: | Size: 5120 | Author: 刘春 | Hits:

[VHDL-FPGA-Verilog] FIFOED_UART

Description: CAL_UART核verilog源码，带FIFO，FIFO深度可设置。-fifoed uart ip core. cal_uart.
Platform: | Size: 6144 | Author: 杨胜尧 | Hits:

[VHDL-FPGA-Verilog] Fifo_lk

Description: 简单好用的Fifo 128x32 Verilog-Fifo 128x32 Verilog
Platform: | Size: 1024 | Author: liukang | Hits:

[VHDL-FPGA-Verilog] fifo_verilog

Description: FIFO的verilog实现,内含PDF说明和已建好工程。-Implementation of FIFO using verilog
Platform: | Size: 744448 | Author: 孙苑 | Hits:
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